1. Technical Field
A semiconductor memory device is disclosed. More specifically, a semiconductor memory device that improves the slope of a signal by reducing the delay of the signal is disclosed. This is achieved by decreasing the load at the global input/output line through the use of repeaters located at the global input/output line.
2. Description of the Related Art
In operation, a semiconductor memory device writes data to a cell, i.e., a data storage space, and reads data from the cell. FIG. 1 is an exemplary schematic diagram that depicts data input/output (IO) lines in a conventional DRAM having four memory banks. Each bank BK0, BK1, BK2, and BK3 includes a row control unit X_CTRL adapted to enable a word line WL, and a column select unit Y_CTRL adapted to enable a column select signal YI in order to designate a cell in the enabled word line WL. The data input/output (10) line is used to read and write data from and to a designated cell, which is determined by enabling the word line WL and the column select signal YI. The IO line includes a segment IO (SIO) line, a local 10 (LIO) line, and a global 10 (GIO) line depending on its position.
In operation, data associated with the cell bit line selected by the column select signal YI are applied to the SIO line. The data applied to the SIO line are applied to the LIO line shared by the SIO lines of cell segment blocks, and then transmitted to the input/output sense amps (IOSA) associated with each bank. In turn, the data sensed by the IOSA are applied to the GIO line. The GIO line is a shared line of memory banks that can be driven by the four banks BK0, BK1, BK2, and BK3.
To perform a read operation, an output driver outputs data via the GIO line to desired data pads DQ0, DQ1, . . . , DQn−1. In the DRAM, when data from the banks BK2 and BK3, which are located farther from the data pads DQ0, DQ1, . . . , DQn−1 than banks BK0 and BK1, are outputted to the data pads DQ0, DQ1, . . . , DQn−1, a delay time is substantially increased due to the long line length of the GIO line.
The increased capacity of the DRAM results in increased chip area. In turn, an increase of the chip area results in an increase in the length of the GIO line. As a result, the increased time delay due to the increased length of the GIO line restricts high speed operations. In addition, when line load is increased, the slope of the GIO signal deteriorates.